Abstract: The authors describes an efficient design and implementation of a decimation filter for high resolution 2nd ΣΔ A/D converter. A new universal multiplier, free VLSI structure is proposed to implement 2, time decimation for half band filters and a high, order invsinc corrector filter, the whole filter is realized without any multiplier or RAM or ROM, and the 2nd ΣΔ A/D converter reaches a 16, bit resolution with low cost.

Key words: 2^nd ΣΔ A/D, multiplier, free structure, decimation Filter

摘要： 描述了一种针对高精度要求的二阶ΣΔ A/D转化器抽取滤波器设计和硬件实现的解决方案;提出了一种能够实现2倍抽取的通用无乘法器硬件实现结构,该结构能有效实施半带滤波器和其他高阶FIR的2倍抽取功能。整个滤波器采用无RAM/ROM技术,实现了低通带文波、窄过渡带、高阻带衰减和高抽取率的系统要求,以很低的硬件代价实现了一个16位精度的ΣΔ A/D转换器。

关键词: 二阶ΣΔA/D转换器, 无乘法器结构, 抽取滤波