Abstract: An improved conditional carry selection (CCS) circuit is proposed in this paper. The new circuit is compared with the conventional conditional carry selection structure for a 4-bit adder. The two circuits were simulated by SPICE under the same condition and the results show that the propagation time of carry and sum (C₃ and S₃)of 4-bit adder are reduced 34.39% and 33.95%, respectively.

Key words: carry chain, adder, CCS, CSS, propagation time

摘要： 介绍了一种对加法器CCS进位链的改进电路，并与没有进行改进的传统的CCS进位链电路进行比较。对这两种电路结构在同样的条件下用SPICE模拟。从实验结果中可以看到，4-bit的加法器单元的进位传输延迟时间缩短了34.39%，并且第4位和的传输延迟时间缩短了33.95%。

关键词: 进位链, 加法器, CCS, CSS, 传输延迟时间