Abstract: Traditional clock routing algorithms can be extended to embrace clock gating by merging minimum switching capacitance node pairs in the bottom-up phase. However, optimizing switching capacitance in the current merging nodes will affect their ancestors' gating chances, which may deteriorate the power consumption. A zero-skew gated clock routing algorithm is proposed to solve this problem. It can reduce the total switching capacitance by evaluating the merging cost of this effect using the result derived from the clock tree generated in the last round. As the result needs to be optimized in iterations, this algorithm employs a simulated annealing technique. At each iteration, the clock tree reconstructs using back-annotated merging cost information and new constraints are generated for optimization in the next round. Experiment results show that this algorithm can achieve up to 23% power reduction compared to the traditional Greedy-DME algorithm.

Key words: gated clock, clock routing, clock skew, low power

摘要： 传统的时钟树布线算法可以扩展应用于门控时钟，例如在自底向上的合并过程中采用最小化合并电容方式。然而，当前点的合并，会影响到上层点的门控情况变化，虽然在局部合并时是最优的，却可能恶化时钟树整体功耗。针对该问题，提出了一种零时钟扭斜门控时钟布线算法，使用上一轮时钟树的布线结果估算上述影响所造成的合并代价变化。由于算法需要多轮反复计算，因此使用模拟退火方法，在每一次循环时重建时钟树结构，通过上一轮反标的合并代价信息进行优化，评估每一轮的结果，并生成新的约束供下一轮使用。实验结果表明，与传统的Greedy-DME算法相比，该算法可以获得至多23%的功耗优化。

关键词: 门控时钟, 时钟布线, 时钟扭斜, 低功耗