Abstract: The authors present a new on-chip jitter measurement method based on cumulative distribution function (CDF) to solve the problem of the mismatch of the delay line, taking up too much chip area and limited by high frequency oscillator signal, which are encountered in measuring multi-GHz clock jitter. The complete circuit is designed and implemented based on the 65 nm CMOS process. The simulation results show that the circuit is able to operate at 2.5 GHz and achieves a timing resolution up to 1 ps.

Key words: timing jitter, built-in jitter measurement (BIJM), time-to-digital (TDC)

摘要： 提出一种基于累积分布函数(CDF)的抖动测量方法, 以解决在测试高频时钟信号抖动中遇到的延迟器件不匹配、占用芯片面积过大和受高频振荡信号限制等问题。采用65 nm CMOS工艺完成了测试电路的设计和功能模拟, 模拟结果表明该电路可用于测量2.5 GHz时钟抖动值, 抖动测量精度达到1 ps。

关键词: 时钟抖动, 内建抖动测试, 时间数字转换器