Abstract: A novel and generic approach is presented to the hardware implementation of the RSA cryptoprocessor in deep submicro (DSM) technology with a redesigned systolic array. With deep submicro technology scaling, integrated circuit performance bottleneck has shifted from logic gates to global interconnection. Besides using the systolic architecture which is popular in hardwarebased RSA systems, a blockbased scheme is proposed to eliminate global signals, with a pipelined bus to convey data globally. The control signals and intermediate results used for sequential multiplications are transmitted by shift registers. All signals, except for the clock signal, are limited in one block or between two adjacent blocks. The Chinese Remainder Theorem (CRT) technique increases the decryption data rate by a factor of four. Two redundant blocks are added to adapt to the online partition of the multiplier and the variation of the length of P and Q in CRT mode. The blockbased global signal transportation scheme and the redundancy scheme are quite different from those of previous works.

Key words: RSA cryptoprocessor, Montgomery modular multiplier, modular exponentiator, public-key infrastructure (PKI), VLSI, systolic array, deep submicro (DSM) technology, Chinese Remainder Theorem (CRT)

摘要： 应用于RSA密码系统的蒙哥马利模乘法算法，在专用集成电路实现时可以采用脉动阵列结构。长比特（1024位以上）数据的全局信号传输和乘法器的动态分割问题，对于RSA密码处理器的速度提高是非常重要的因素。作者提出一种基于模块的全局信号广播策略，减少全局信号的影响：通过采用流水化的总线传送全局数据；通过移位寄存器传送控制信号以及用于连续的乘法的中间结果。除了全局时钟之外的信号都被限定在一个模块内部或者相邻的2个模块之间。中国剩余定理（CRT）的采用，将解密速度提高了近4倍，作者提出一种冗余结构，使得在采用CRT时乘法器可以有效的进行动态分割。

关键词: RSA密码处理器, 蒙哥马利模乘法器, 模乘幂运算器, 公钥基础设施, 超大规模集成电路, 脉动阵列, 深亚微米技术, 中国剩余定理