Acta Scientiarum Naturalium Universitatis Pekinensis

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Design Optimization and Implementation of Carrier Tracking Loop for High Sensitivity GPS Receivers

WU Lingjuan, CUI Yingying, LU Weijun, YU Dunshan   

  1. Department of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing 100871;
  • Received:2010-07-29 Online:2011-09-20 Published:2011-09-20



  1. 北京大学信息科学技术学院微电子学系, 北京 100871;

Abstract: This paper presents the design, optimization and implementation of GPS carrier tracking loop based on high sensitivity GPS base band signal processor research topic. The phase detector, loop error sources and loop parameters are first optimized to improve the tracking sensitivity and then the phase lock loop assisted by frequency lock loop circuit structure is applied. The circuit is optimized and timing-sharing technology is used for the modules including several multipliers and dividers to reduce resource consumption and save chip area. The authors implement the designed GPS carrier tracking loop in Verilog and complete the logic and functional simulation in Modelsim with RTL level code. The FPGA board verification platform is established and the performance test is carried out using GPS L1 band signal source. The test result shows that the tracking sensitivity can reach 25 dB-Hz and chip area of the single channel carrier tracking loop is 425555μm2 in SMIC 0.18μm technology using Design Complier.

Key words: GPS, high sensitivity, carrier tracking, PLL, FLL

摘要: 基于高灵敏度GPS基带信号处理器, 设计优化并实现了GPS载波跟踪环路。为了提高跟踪灵敏度, 对鉴相器的性能、环路误差、环路参数进行了分析优化, 并采用锁频环辅助锁相环结构, 同时对于需要多个乘法器、除法器的模块采用分时共享技术, 降低了资源消耗减小芯片面积。用Verilog硬件描述语言实现了所设计的载波跟踪环路, 在ModelSim中完成了RTL级代码的逻辑和功能仿真, 搭建了FPGA开发板验证平台, 并使用GPS L1波段信号源进行性能测试。测试结果表明所设计的载波跟踪环路可达到25 dB-Hz的跟踪灵敏度。单通道载波跟踪环路基于SMIC 0.18μm工艺, Design Complier的逻辑综合面积为425555μm2

关键词: 全球定位系统(GPS), 高灵敏度, 载波跟踪, 锁相环(PLL), 锁频环(FLL)

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