A Novel Latched Comparator with Low Kickback Noise

Acta Scientiarum Naturalium Universitatis Pekinensis

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A Novel Latched Comparator with Low Kickback Noise

ZHANG Xin¹, YU Dunshan, SHENG Shimin

Institute of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing,100871; ¹E-mail: zhangxin@ime.pku.edu.cn

Received:2005-12-09 Online:2006-09-20 Published:2006-09-20

一种新型低kickback噪声的闩锁型比较器

张信¹,于敦山,盛世敏

北京大学信息科学技术学院微电子研究所，北京，100871；¹E-mail: zhangxin@ime.pku.edu.cn

Abstract

Abstract: A new latched comparator architecture was proposed. Because of its very low kickback noise feature, it is especially suitable for differential analog-to-digital converters (ADCs). Simulated results of the proposed circuit in a 0.35μm standard CMOS technology show that this comparator achieves a sampling speed of 400 Ms/s at 3.3V supply, with a kickback noise 88% lower than conventional schemes.

Key words: analog-to-digital(A/D) conversion, parallel ADC, high-speed comparators, kickback noise

摘要： 提出了一种新的闩锁型比较器结构。由于它的低kickback噪声特性，此比较器特别适合应用于差分模拟－数字转换器(ADCs)。电路采用标准 0.35μm 的工艺进行模拟，结果显示此比较器在 3.3V 电源下采样频率为 400Ms/s，并且kickback噪声比传统结构减少了88%。

关键词: 模拟－数字转换, 平行ADC, 高速比较器, kickback噪声

CLC Number:

TN432

ZHANG Xin,YU Dunshan,SHENG Shimin. A Novel Latched Comparator with Low Kickback Noise[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

张信,于敦山,盛世敏. 一种新型低kickback噪声的闩锁型比较器[J]. 北京大学学报（自然科学版）.

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A Novel Latched Comparator with Low Kickback Noise

一种新型低kickback噪声的闩锁型比较器

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